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rej03g1782-0401 rev. 4.01 page 1 of 27 jun 17, 2010 target specification datasheet r2j20702np peak current mode synchronous buck controller with power mos fets description this all-in-one sip for pol (point-of-load) applications is a multi-chip module incorporating a high-side mos fet, low-side mos fet, and pwm controller in a single qfn p ackage. the on and off timin g of the power mos fet is optimized by the built-in driver circuit, making this devi ce suitable for large-current high-efficiency buck converters. in a simple peak-current mode topology, stable operation is obtained in a closed power loop, and a fast converter is easily realized with the add ition of simple components. furthermore, the same topology can be applied to realize converters for parallel synchronized operation with current sharing, and two-phase operation. the package also incorporates a high-sid e bootstrap schottky barrier diode (sbd), eliminating the need for an external sbd for this purpose. features ? three chips in one package for high-efficiency and space saving ? large average output current (40 a) ? wide input voltage range: 8 to 14 v ? 0.6 v reference voltage accurate to within 1% ? wide programmable switching frequency: 200 khz to 1 mhz ? fast response by peak-current-mode topology. ? simple current sharing (up to five modules in parallel) ? two-phase operation in parallel operation ? built-in sbd for boot strapping ? on/off control ? hiccup operation under over load condition ? tracking function ? thin small package: 56-pin qfn (8 mm ? 8 mm) ? terminal pb-free/halogen-free applications ? network equipment ? telecommunications equipment ? servers ? pol modules typical characteristic curve 75 80 85 90 95 0 5 10 15 20 25 30 4035 efficiency (%) iout (a) vin = 12 v vout = 1.8 v l = 320 nh co = 600 f frequency = 500 khz no airflow ta = 27c rej03g1782-0401 rev.4.01 jun 17, 2010
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 2 of 27 jun 17, 2010 application circuit example vin pgnd sw boot reg5 on/off sync iref ct trk-ss fb eo sgnd ishare ramp cs controller chip vcin drv5 vin (8 v to 14 v) reg5 vout (1.8 v)
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 3 of 27 jun 17, 2010 block diagram 50 k 50 k active current s ensin g s r q q ocp comparator e rror a mp. o s c p u lse g enerator res m a x. duty ( bi-lateral ) res m a x. duty 50 ns 55 n s blanki n g uvl o 5 v ( 4 %) r e g u l ator o n/o ff g ate d r ive l o gic c i rcui t ocp pwm o n/o ff b oot reg5 o n/o ff iref c t sync trk-ss fb e o drv5 idh idh 22000 sbd vout current s ens e comparator reg5 1.5 v ocp hiccup control 0 . 6 v (1%) reg5 ocp reg good on/off (1024 pu lse s blank) vcin 0 . 1 v 4 90 a s u p ervisor 5 . 25 v ( 4 %) r e g u l ator drv5 v in ishare r a mp c s pgnd sw sgnd 8 v to 1 4 v vout r eference current g enerator reg good reg good
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 4 of 27 jun 17, 2010 pin arrangement (top view) fb ishare eo iref reg5 sgnd vcin boot sw vin vin vin vin vin pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd sw trk-ss ct vin ramp vin vin cs vin sgnd vin drv5 sw on/off pgnd sync pgnd sw pgnd sw pgnd sw pgnd sw pgnd sw sw sw package: 56-pin qfn (8 mm 8 mm, 0.5-mm pin pitch) sgnd vin 56 43 44 45 46 47 48 49 50 51 52 53 54 55 pgnd vin 15 28 27 26 25 24 23 22 21 20 19 18 17 16 sw 1 14 13 12 11 10 9 8 7 6 5 4 3 2 sw pgnd 42 29 30 31 32 33 3 4 35 36 37 38 39 40 41 note: all die-pads (three pads in total) should be soldered to pcb.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 5 of 27 jun 17, 2010 pin description pin name pin no. description remarks vin 10 to 20 input voltage for the buck converter. sw 9, 21, 40 to 48 switching node. connect a choke coil between the sw pin and dc output node of the converter. pgnd 22 to 39 ground of the power stage. should be externally connected to sgnd. sgnd 6, 52 ground of the ic chip. should be externally connected to pgnd. vcin 7 input voltage for the control circui t. should be externally connected to vin. boot 8 bootstrap voltage pin. a bootstrap capacitor should be connected between the boot and sw pin. to be supplied +5 v through the internal sbd. reg5 5 +5 v logic power-supply output. requires decoupling from the gnd plane by a capacitance 0.1 ? f. on/off 50 signal disable pin. disabled when on/off pin is in the low state. iref 4 reference current generator for the ic. should be connected via 27 k ? to the sgnd pin. ct 55 timing capacitor pin for the oscillator. this pin has a select function for operation in slave mode. if the pin voltage is <1 v or >4 v, the ic operates in slave mode. sync 49 i/o pin for synchronous operation. trk-ss 56 start-up timing control input. fb 1 feedback voltage input for the closed loop. when ic works as a slave module in multiphase power supply, fb pin should connected to reg5 pin. eo 3 error amplifier output pin. requires connection to an rc circuit for loop compensation. ishare 2 for current-sharing bus. simply connect the ishare pins of all devices to get balanced current. ramp 54 ramp signal input pin for peak current mode pwm control. cs 53 current output pin of active current sensing circuit. appropriate resistance is required between cs and the gnd plane. drv5 51 +5.25 v generator output for driving power mos fets. requires decoupling from the gnd plane by a capacitance from 0.1 ? f to 1.0 ? f.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 6 of 27 jun 17, 2010 absolute maximum ratings (ta = 25c) item symbol rating unit note pt(25) 25 1 power dissipation pt(110) 8 w 1 average output current iout 40 a vin (dc), vcin (dc) ?0.3 to +16 2 input voltage vin (ac), vcin (ac) 20 v 2, 4 vsw (dc) 16 2 switch node voltage vsw (ac) 20 v 2, 4 vboot (dc) 22 2 boot pin voltage vboot (ac) 25 v 2, 4 on/off pin voltage von/off ?0.3 to vin v 2 sync pin voltage vsync ?0.3 to +5.5 v 2 voltage on other pins vic ?0.3 to (reg5 + 0.3) v 2 reg5 current ireg5 ?10 to 0 ma 3 ishare current ishare ?500 to 0 ? a 3 trk-ss dc current itrk 0 to 1 ma 3 iref current iref ?120 to 0 ? a 3 eo sink current ieo 0 to 2 ma 3 operating junction temperatur e tj-opr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. pt(25) represents a pcb temper ature of 25c, and pt(110) represents 110c. 2. rated voltages are relative to voltages on the sgnd and pgnd pins. 3. for rated current, (+) i ndicates inflow to the chip and (?) indicates outflow. 4. ratings for which ?ac? is indicated are limited to within 100 ns. pcb temperature (c) average output current (a) safe operating area 50 35 40 45 0 5 10 15 20 30 25 0 25 50 75 125 175 150 100 vin = 12 v vout = 1.5 v fsw = 465 khz l = 0.32 h
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 7 of 27 jun 17, 2010 electrical characteristics (ta = 25c, vin = vcin = 12 v, unless otherwise specified) item symbol min typ max unit test conditions vin start threshold vh 6.8 7.2 7.6 v vin shutdown threshold vl 6.45 6.85 7.25 v uvlo hysteresis duvl ? 0.35 * 1 ? v input bias current iin 20 50 80 ma ct = 68 pf, duty cycle = 50% supply input shutdown current isd 1.3 2.3 3.3 ma on/off = 0 v output voltage vr eg 4.8 5.0 5.2 v line regulation vreg-line ?5 0 +5 mv vin = 10 to 16 v 5-v regulator load regulation vreg-load ?8 ?3 +2 mv ireg = 0 to 10 ma 5.25-v regulator output voltage vdrv 5.04 5.25 5.46 v disable threshold voff 1.0 1.3 1.6 v enable threshold von 2.0 2.5 3.0 v remote on/off input current ion/ off 0.5 2.0 5.0 ? a von/off = 1 v reference current generator iref pin voltage viref 2. 6 2.7 2.8 v riref = 27 k ? ct oscillating frequency fct ? 930 * 1 ? khz ct = 68 pf sw switching frequency fsw 418 465 512 khz ct = 68 pf ct higher trip voltage vhct ? 3 * 1 ? v ct = 68 pf ct lower trip voltage vlct ? 2 * 1 ? v ct = 68 pf ct source current ict-src ?176 ?160 ?144 ? a ct = 1.5 v ct sink current ict-snk 144 160 176 ? a ct = 3.5 v ct threshold for two- phase operation vct-two 3.6 4.0 4.4 v oscillator ct threshold for synchronous operation vct-one 0.8 1.0 1.2 v sync frequency fsync 418 465 512 khz ct = 68 pf sync high voltage vh-sync 4.0 5.0 ? v rsync = 51 k ? to gnd sync low voltage vl-sync 0 ? 1.0 v rsync = 51 k ? to reg5 sync and pulse generator sync input threshold vsync 1.0 2.0 3.0 v ct = 0 v or 5 v feedback voltage vfb 594 600 606 mv trk-ss = 1 v input bias current ifb ?0.1 0 +0.1 ? a fb = 0.6 v output source current io-src 150 200 250 ? a eo = 4 v, fb = 0 v output sink transient current io-snk 5.0 10.6 19.0 ma eo = 1 v, fb = 1 v voltage gain av ? 80 * 1 ? db band width bw ? 15 * 1 ? mhz error amplifier resistance connected to the ishare pin rshare 70 100 130 k ? eo = 0 v. ishare = 1 v note: 1. these are reference values for desig n and have not been 100% tested in production.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 8 of 27 jun 17, 2010 (ta = 25c, vin = vcin = 12 v, unless otherwise specified) item symbol min typ max unit test conditions cs current ratio idh/ics ? 22000 * 1 ? ? leading edge blanking time tld ? 55 * 1 ? ns cs comparator delay to output td-cs ? 50 * 1 ? ns ocp comparator threshold on cs pin vocp 1.43 1.5 1.57 v hiccup interval tocp 1.98 2.20 2.42 ms ct = 68 pf ramp offset voltage vramp-dc 79 94 109 mv current sense cs offset current ics-dc ? 490 * 1 ? ? a cs = 0 v note: 1. these are reference values for desig n and have not been 100% tested in production.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 9 of 27 jun 17, 2010 description of operation peak current control the control ic operates in a current-programmed control mode, in which the output of the converter is controlled by the choice of the peak current from the hi gh-side mos fet. the current from this mos fet is sensed by an active current-sensing circuit (acs), the output current of which is 1/22000 (54 ppm) of the mos fet current. the acs current is then converted to a certain voltage by the external resistor on the cs pin. the cs voltage is fed to the ramp pin by an external connection, then compared with the current-control signal which is determined from the error amplifier output voltage (eo) via an npn transistor and resistor network. to start with, the res pulse from the pulse generator resets a latch, then the high-side mos fet is turned on. the latch output (q bar) is toggled when th e voltage on ramp reaches the level of the current-control signal on eo, the high-side mos fet is turned off, and the low-side mos fet is turned off after a certain dead-time interval. the ic remains in this state until the arrival of the next res pulse. since current information is used in the control loop, loop compensation design for the converter is simple and easy. maximum duty-cycle limitation if the current-sense comparator output is not toggled 50-ns prior to the arrival of the next res pulse, an internal maximum duty pulse is generated and forces toggling of the sr latch. so, the duty cycle of the high-side mos fet is limited by the maximum duty period. the maximum duty period of the high-side mos fet depends on its switching frequency. maximum duty period = 1 ? 50 ns ? fsw ocp hiccup operation once the voltage of cs exceeds 1.5 v, ocp hiccup circuit disables switching operation of the ic and mos fets. internal circuitry also pulls the trk-ss pin down to sgnd. the ic is turned off for a period of 1024 res pulses; after this has elapsed, switching operation of the ic is restarted from the soft-start state. uvlo and on/off control when vin (=vcin) is below the start-up voltage, that is, is in the uvlo condition, functioning of the ic is disabled. the oscillator is turned off, both high- and low-side mos fets are turned off, and the trk-ss pin is pulled down. furthermore, if the on/off pin is in the low state or left open, functioning of the ic is disabled and both mos fets are turned off. relationship between fb pin and a pull-down mos fet on trk-ss pin when r2j20702np works as a slave modul e in a multi-phase power supply, fb pi n should be connected to reg5 pin. in this case, the pull-down mos fet on trk-ss pin does not be turned on.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 10 of 27 jun 17, 2010 oscillator and pulse generator the frequency of oscillation is set by the value of the external capacitor connected to the ct pin. this frequency is twice as high as the actual switchin g frequency. the frequencies are determined by the following equations: oscillator frequency; fct = 160 ? a / {2 ? (ct(f) + 18 pf) ? 1 v} (in hz) switching frequency; fsw = 0.5 ? fct (hz) when the chip is operating in standalone mode or as the ma ster chip for parallel operation, it requires a capacitor on the ct pin. in this case, the sync pin outputs a synchronization signal with a frequency of fsw. in operation as a slave chip, the ct pin must be connected to sgnd or reg5, after which it acts as an input pin for the synchronized operation by external clock. the internal ci rcuit is synchronized its rising edge when ct<0.8 v, falling edge when ct>4.4 v. in two-phase operation in parallel configuration, the ct pin should be at a voltage over 4.4 v. mode item standalone master slave ?0 slave ?180 ct pin has a cap. has a cap. < 0.8 v > 4.4 v sync pin output mode output mode input mode input mode synchronizing trigger ? ? rising falling the internal res pulse and maximum duty-cycle-control pul ses are produced from the signal at half the oscillator frequency in standalone and master operating modes. in slave mode, internal pulses are produced from the externally supplied input signal on the sync pin. current sharing it is easy to obtain balanced-current operation in a parallel configuration due to the application of peak current control. to obtain current-sharing operation, simply tie the buffered error-amplifier outputs of all of the devices (ishare pins) together. no more than five devices can operate in parallel. soft start both simple soft starting and tracking star t-up can be realized with the setup of the trk-ss pin provided for soft-starts. the error amplifier has three inputs, two of which are designe d to give priority to low-level non-inverting inputs for the amplifier. all that is required to realize soft-start opera tion is to simply attach an rc charging circuit to the trk-ss pin. the soft-start period is determined by the following equation, with c and r as the values for the rc charging circuit attached to the trk-ss pin. tss = ?c r ln (1 ? 0.6 v / reg5) (s)
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 11 of 27 jun 17, 2010 application example start-up settings case 1) standalone or master chip in parallel operation with the rc network on the trk-ss pin, the voltage on the pin should ramp up slowly. 0.6 v tss = ? cr l n (1 ? 0.6 v / 5 v) (s) on/off reg5 trk-ss r trk-ss c vout case 2) coincident tracking the trs-ss signal for channel two is the voltage from vout1 after division by a resistor network. vout1 must be greater than vout2. cross-talk is not generated between the channels. reg5 trk-ss fb channel 1 sw r vout1 c r1 reg5 trk-ss fb channel 2 sw from vout1 r2 r3 vout2 r4 r3 vout2 (nominal ) = 0.6 v (r3 + r4) / r4 vout1 (nominal ) = 0.6 v (r1 + r2) / r2 r4 vout1 output voltage vout2 time
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 12 of 27 jun 17, 2010 case 3) retiometric tracking the trs-ss of channel two is tied to trk-ss of channel 1. no cross talk is observed between the channels. reg5 trk-ss fb channel 1 sw r vout1 c r c r1 reg5 trk-ss fb channel 1 sw r2 vout2 r3 vout2 (nominal) = 0.6 v (r3 + r4) / r4 vout1 (nominal) = 0.6 v (r1 + r2) / r2 r4 vout1 output voltage vout2 time
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 13 of 27 jun 17, 2010 case 4) current sharing or two-phase operation in the case of master?slave operatio n, the trk-ss pin on the master de vice should be attached to an rc network for soft starts. trk-ss pins of slave devices should be tied to the master?s trk-ss pin. the error amplifiers on the slave devices can be disabled by pulling up the corresponding fb pins to reg5, and the slave devices do not require loop-compensation networks. reg5 trk-ss ishare ishare fb channel 1 (master) sw r vout1 c r c r1 reg5 trk-ss fb ct ct channel 2 (slave) sw r2 vout (nominal) = 0.6 v (r1 + r2) / r2 to sgnd (for current sharing and synchronized operation) to reg5 (for current sharing and two-phase operation) choice of the resistance of cs pin the cs pin is a current-output pin. a current 1/22000 of that of the high-side mos fet flows through this pin, which also has a dc current offset of 490 ? a. the converter?s maximum current is determined by the voltage on the cs pin, i.e. 1.5 v, and by the value of the external resistor attached to this pin. the resistance is determined as shown below. specification: l = 360 nh, vin = 12 v, vout = 1.8 v, fsw = 500 kh z, iout(max) = 30 a current through the choke coil is ilpp = (vin ? vout) ? vout / (l ? vin ? fsw) = 8.5 a (p-p) peak choke current is the current wh en io is at its maximum, i.e. ilmax = io(max) + 0.5 ? ilpp = 30a + 4.25a = 34.25 a maximum cs pin output current is; icsmax = ilmax / 22000 + ics-dc = 34.25 a / 22000 + 490 ? a = 2.047 ma the ideal resistance for attachment to the cs pin is rcs = vcl / icsmax =1.5 v / 2.047 ma = 733 ? therefore choose 750 ? as the value of the resistor for attachment to the cs pin.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 14 of 27 jun 17, 2010 output voltage setting the error amplifier of the device has an accurate 0.6 v reference voltage. feedback thus leads to a voltage of about 0.6 v on the fb pin once the converter system has stabilized, so the output voltage is vout = 0.6 v ? (r1 + r2) / r2 reg5 trk-ss fb sw r vout c r1 r2 ct loop compensation peak-current control makes design in terms of phase margin s easier than is the case with voltage control. this is because of differences between the characteristics of the pwm modulator and power stage in the two methods. figures 1 and 2 show the behavior of the pwm modulator and power stage in the cases of voltage control and peak current control, respectively. freq. (hz) freq. (hz) ?180 0 ?40 db/dec gain (db) phase (deg) ?20 db/dec gain (db) freq. (hz) 0 phase (deg) ?90 ?180 freq. (hz) figure 1 bode plot of modulator + power stage (voltage mode) figure 2 bode plot of modulator + power stage (peak curent mode) feed-forward current to the modulator in the case of peak-current control means that the system is single pole, so we see a ?20 db/decade cutoff and phase margin of 90 in the bode plot. in voltage control, the system configures a two- pole pole system. that is why rather co mplicated loop compensation of the error am plifier is required, such as type-iii compensation. the design of effective compensation is thus much simpler in the case of peak-current control (refer to figure 3).
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 15 of 27 jun 17, 2010 r2 r1 vout amplifier output: to current -sense comparato r 50 k 50 k 0.6 v reference fb eo r fcf figure 3 error amplifier compensation design example specification: l = 360 nh, co = 600 ? f, fsw = 500 khz, vin = 12 v, vout = 1.8 v, r1 = 2 k ? , r2 = 1 k ? , rcs = 750 ? 1. flat-band gain of error amplifier the flat-band gain is; af = rf / (r1 // r2) / 2 ? {r2 / (r1 + r2)} hence, rf = 2 ? af ? r1 ?? (1) in the bode plot, the total gain should be less than 1 (0 db) at the switching frequency. the total gain at fsw (= asw) depends on the flat-band gain, so af should be expressed as follows. af = asw ? 2 ? ? fsw ? co ? rcs / nt ?? (2) here, nt = idh / ics = 22000 in the typical way, the value chosen for asw is in the range from 0.1 to 0.5, since this produces a stable control loop. the transient response will be faster if a larger as w is adopted ,but the system might be unstable. we choose 0.25 for asw in the example below. af = 0.25 ? 2 ? ? 500 khz ? 600 ? f ? 750 ? / 22000 = 16.06 rf = 2 ? 16.06 ? 2 k ? = 64.240 k ? therefore, we select a value of 62 k ? for rf. 2. selecting the cf value to de termine the frequency of the zero the frequency of the zero established by cf and rf is about ten times the frequency of the pole for the power stage and modulator. we must start with the dc gain of the power stage and modulator. a 0 = (3) 2 nt / rcs l vin fsw sqrt {vin 2 ? 8 l vin fsw (vcs0 nt / rcs) } here vcs0 is the peak ac voltage on the cs pin when the load current is zero, thus vcs0 = 0.5 ? rcs ? (vin ? vout) ? vout / (l ? vin ? fsw) / 22000 ?? (4) = 0.5 ? 750 ? ? (12 v ? 1.8 v) ? 1.8 v / (360 nh ? 12 v ? 500 khz) / 22000 = 0.145 v
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 16 of 27 jun 17, 2010 equation (3) a 0 = (3) 2 nt / rcs l vin fsw sqrt {vin 2 ? 8 l vin fsw (vcs0 nt / rcs) } = 2 22000 / 750 360 nh 12 v 500 khz sqrt {12 v 2 ? 8 360 nh 12 v 500 khz (0.145 v 22000 / 750 ) } = 126.72 sqrt {70.502} = 15.092 the frequency of the pole established by the power stage and modulator is f0 = nt / (2 ? ? co ? rcs ? a0) ?? (5) thus, f0 = 22000 / (2 ? ? 600 ? f ? 750 ? ? 15.092) = 516 khz therefore, the frequency of the zero established by cf and rf is fzero = 10 ? f0 = 5.16 khz cf = (2 ? ? fzero ? rf) ?1 = (2 ? ? 5.16 khz ? 62 k ? ) ?1 = 497 pf therefore, we select the value 510 pf for cf. basically, the transient response is faster when cf is smaller, but too small a value will make the system-loop unstable. f0 fzero bw/af error amp. unity g ain frequency bw af a0 fsw open l oop converter w/ error amp. compensation power s tage and modulator gain (db) freq. (hz) ?20 db/dec ?40 db/d ec ?20 db/dec asw figure 4
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 17 of 27 jun 17, 2010 study of vout accuracy the nominal output voltage is calculated as vout = vfb ? (r1 + r2) / r2 ?? (6) here, the typical feedback voltage is 0.6 v. reg5 trk-ss fb ct sw r vout c r1 r2 the accuracy of vout is strongly dependent on the variation of vfb, r1 and r2. vfb has a variation of 1% and resistance intrinsically has a certain variation. when we ta ke the variation in resistance into account, equation (6) is extended to prod uce equation (7). vout = r1 k1 + r2 k2 r2 k2 vfb = r1 k1 / k2 + r2 r2 vfb (7) here, k1 and k2 are coefficients. both are 1.00 in the ideal case. by equation (6), r1 is chosen as vfb (typical) vout (typical) r1 = ? 1 r 2 (8) substituting this expression for r1 into equation (7) yields the following. vfb (typical) vout (typical) vout = vfb ? 1 + 1 (9) k1 k2 therefore, variation in vout is expressed as vfb (typical) vout (typical) k1 k2 = ? 1 + 1 ? 1 100 (%) (10) vout (typical) vfb vout vout (typical)
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 18 of 27 jun 17, 2010 the accuracy of vout can be estimated by using equation (10). for example, if vout (typical) = 1.8 v, resistance variation is 1% (i.e. k1, k2 = 1.01 and 0.99), and vfb = 594 mv to 606 mv: vfb (typical) vout (typical) k1 k2 = ? 1 + 1 ? 1 100 (%) (10) = ? 1 + 1 ? 1 100 (%) = ? 1 + 1 ? 1 100 (%) vout (typical) vfb vout vout (typical) 1.8 v 600 mv 1.01 0.99 606 mv 1.8 v = 2.36% or 1.8 v 600 mv 0.99 1.01 594 mv 1.8 v = ?2.31% therefore, the output accuracy will be ? 2.3% under the above conditions. figure 5 shows the relationshi p between the accuracy of the resistance an d the accuracy of the output voltage. the resistor value must have an accuracy of 0.5% if the variation in output voltage from the system is to be kept within two percent across the voltage range from 0.6 to 3.3 v. ?3 ?2 ?1 0 1 2 3 0.51 .01 .52 .02 .53 .03 .5 vout (typical) vout accuracy (%) r = 0.5% r = 1% figure 5 vout accuracy vs. vout set voltage
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 19 of 27 jun 17, 2010 current sharing simply tie the ishare pins together vout device 1 device 2 device n (up to 5) ishare sync ct reg5 ishare sync c t reg5 ishare sync c t reg5 external synchronization simply tie the ct pin to gnd external clock 5 v 0 v external clock; frequency range: 200 khz to 1 mh z minimum pulse width: 100 ns maximum pulse d uty cycle: 90% ishare sync c treg 5 vout
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 20 of 27 jun 17, 2010 current sharing and synchronization tie the ishare and sync pins together vout device 1 (master) device 2 device n (up to 5) ishare sync ct reg5 ishare sync c t reg5 ishare sync c t reg5 two-phase operation tie the ishare and sync pins together. il1 ishare sync c t reg5 vout device 1 (master) il2 ishare sync c t reg5 device 2 (slave) 2.4 k il1 il2
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 21 of 27 jun 17, 2010 timing chart peak current control (eo-vbe) / 2 (internal signal) eo ramp tld 50 ns (typ.) max. duty (internal signal) res (internal signal) 50 ns (typ.) 0 v vin sw 0 v the high-side mos fet is turned off by the max. duty signal. note: propagation delay is ignored.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 22 of 27 jun 17, 2010 oscillator and pulse generator 1. standalone operation or operation as the master chip in a parallel configuration with other chips. 3 v ct sync 2 v 5 v 0 v max. duty (internal signal) 50 ns (typ.) res (internal signal) note: propagation delay is ignored. frequency of oscillation for ct: fct = (h z) 160 a 2 (ct(f) + 18 pf ) 1 v switching frequency fsw = 0.5 ? fct (hz) frequency setting range (for fsw): 200 khz to 1 mhz (i.e. 400 khz to 2 mhz for fct)
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 23 of 27 jun 17, 2010 2. operation as a slave chip (simple synchronous operation) ct sync (input) max. duty (interna l signal) res (interna l signal) 50 ns (typ.) should be pulle d down to or below 0.8 v. 0.8 v 0 v 5 v 0 v sync frequency range: 200 khz to 1 mhz note: propagation delay is ignored. 3. operation as a slave chip in a parallel configuration (two-phase operation) ct sync (input) max. duty (interna l signal) res (interna l signal) 50 ns (typ.) should be pulled up to at least 4.4 v. 5 v 4.4 v 5 v 0 v sync frequency range: 200 khz to 1 mhz note: propagation delay is ignored.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 24 of 27 jun 17, 2010 hiccup operation when the over-current limit (ocl) is reached cs 0 v 1.5 v normal operation 1024 pulses skippe d 1024 pulses skippe d trk-ss detected ocl note: propagation delay is ignored.
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 25 of 27 jun 17, 2010 main characteristics 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.7 ?50 ? 25 0 100 125 150 temperature (c) vh vs. temperature vh (v) 25 50 75 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 ?50 ? 25 0 100 125 150 temperature ( c) vl vs. temperature vreg vs. temperature vfb vs. temperature vl (v) vreg (v) vfb ( mv) 25 50 75 ?50 ? 25 0 100 125 150 temperature (c) 25 50 75 ?50 ? 25 0 100 125 150 temperature ( c) 25 50 75 4.90 4.95 5.00 5.05 5.10 590 592 594 596 598 600 602 604 606 608 610
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 26 of 27 jun 17, 2010 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 430 440 450 460 470 480 490 500 ?50 ? 25 0 100 125 150 temperature (c) fsync vs. temperature fsync (khz) 25 50 75 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 ?50 ? 25 0 100 125 150 temperature ( c) von vs. temperature voff vs. temperature fsync vs. ct von (v) voff (v) fsync (khz) 25 50 75 ?50 ? 25 0 100 125 150 temperature (c) 25 50 75 10 500 ct (pf) 100 100 1000 2000 ct = 68 pf
r2j20702np target specification rej03g1782-0401 rev. 4.01 page 27 of 27 jun 17, 2010 package dimensions y a z e l p 3.0 0.0 z d a 1 c c 1 14 15 1 56 3.0 0.0 28 29 43 42 3.0 0.3 1.0 3.0 b b 1 0.4 c 8. 058. 007.95 8. 058. 007.95 ma xno mmin dimension in millimeters symbol reference 0.50 0.22 0.20 0. 17 0.27 0.20 0.005 0.25 0.23 0.30 0.400 . 50 0.60 0.95 0.05 8. 308.20 8.10 8.20 0.75 0.75 8.10 8.30 t y 1 l p z e z d y x b 1 b a a 2 e d a 1 e c 1 h d c h e e p-hvqfn56-8x8-0.50 0.2g mass[typ.] ? pvqn0056ka-a renesas code jeita package code previous code 0.4 1.0 29 42 28 43 e d 56 1 index mark h e h d 15 14 ordering information part name quantity shipping container r2j20702np#g3 2500 pcs taping reel
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